For demanding military applications like radar and SIGINT, OpenVPX offers many performance advantages. A custom backplane topology opens up many options that go beyond “standard” profiles.
BRIAN ROBERTS, SENIOR DESIGNER DAWN, VME PRODUCTS
OpenVPX is a robust embedded computing standard, developed to meet the needs of demanding defense and industrial applications. A primary goal during the definition of OpenVPX was that it facilitates multivendor COTS system-level interoperability including modules, backplanes and development chassis. Since embedded defense systems must often be developed and deployed rapidly, it is very important that potential conflicts are eliminated as quickly as possible during the design phase.
Established by the VITA Standards Organization and formally designated as ANSI/VITA 65.0, OpenVPX references other VITA standards to define a comprehensive systems architecture including mechanical specifications for modules, connector descriptions, thermal characteristics, communications protocols, utility and power definitions. It also defines a multiplane architecture approach for communication between system components, including support for several high-bandwidth switch fabric protocols including 10 GbE, PCI Express, Serial RapidIO and SATA for nonvolatile memory. New revisions of these standards are pushing the limits of differential copper pairs; OpenVPX provides for coax and fiber optic connections to support higher-speed data and other signal formats, but the current generation of systems must still rely on copper connections throughout the backplane.
Figure 1
Backplane topologies are identified as Central or “Star,” Distributed or “Mesh,” and Hybrid, a combination of VME slots and VPX slots.
Many Topology Options
An OpenVPX backplane can be configured into many network topologies such as mesh, star, dual-star, ring or daisy chain. These on-backplane networks permit multiple signals to be routed such that several cards can talk to each other simultaneously, achieving an aggregate bandwidth well over 100 Gbytes/s. OpenVPX uses a concept called “profiles” to define the choices for switch fabrics and other technologies. In a system chassis, there are slot profiles that define the mapping of I/O onto the backplane connectors; Payload, Peripheral, Switch, Storage and Bridge are types of slot profiles, with multiple unique and specific profiles organized under each type. Profile parameters are used to further describe properties of a backplane profile.
An OpenVPX backplane profile is a physical definition of a backplane implementation that includes details such as the number and type of slots that are implemented and the topologies used to interconnect them. Ultimately a backplane profile is a description of channels and buses that interconnect slots and other physical entities in a backplane, describing the fabric interconnections from slot to slot. Backplane topologies are identified as Central or “Star,” Distributed or “Mesh,” and Hybrid, a combination of VME slots and VPX slots (Figure 1).
Components from different vendors that adhere to the same OpenVPX profile can be configured into functional systems. This critical characteristic of OpenVPX delivers the benefits of interoperability, straightforward technical upgrades and competition-driven cost containment to the end users of systems, such as the Department of Defense. However, the devil is in the details, as the large number of parameters involved in each profile make matching component profiles a demanding design function.
Mission-Critical Systems
The flexibility offered by the wide range of OpenVPX profiles allows designers to optimize the communication topology between slots within a system’s backplane, delivering tremendous improvements in the performance of real-time applications. Slots can be designed to accept the best I/O modules for a specific application and the number of those slots also matched to application needs. Similarly, the number of processing modules is set to meet the performance requirements, and then the connections between all these modules are designed to match the applications processing style and deliver maximum sensor processing throughput.
However, implementing this level of optimized topology can be a complex and time-consuming task, constrained by a number of factors. In the defense arena, an example would be a computing system providing image processing on an unmanned aerial vehicle (UAV), using a set of high-performance computing modules and multiple input channels from image sensors.
This computing system must deliver real-time performance while staying within clearly defined Size, Weight and Power (SWaP) constraints that are defined by both the characteristics of the UAV and type of missions it must perform. The system design must make optimal use of every slot and every communication link between the modules in the slots. OpenVPX profiles enable this optimization, but a cookie cutter, one-size-fits-all approach is not going to work.
There is also the real-world challenge of design changes. To go back to the UAV example, it may be that after the system design is already underway, a high-level decision is made to utilize a new, advanced type of sensor with a much greater input bandwidth. This, in turn, drives a change in the backplane profile to accommodate the added bandwidth; somehow, the backplane must be adjusted in accordance with a new OpenVPX profile.
Figure 2
This advanced implementation improves the signal integrity between system cards beyond the requirements of the PCI Express, Serial Rapid I/O and 10Gbit (XAUI) Ethernet standards.
Customized Backplanes
A long-standing approach to customizing system backplanes is the use of PCB overlays, which fit over an existing backplane, linking backplane pins to the new, desired and optimized connection topology. This is an effective way to modify an existing design quickly, saving time and money.
However, as communications fabrics move into the 5 GHz range, a new set of challenges arise. The impedance variations imposed by the high-performance OpenVPX multi-gig differential connector create significant issues when attached to a standard overlay. There are also cost issues involved in creating traditional overlays for complex OpenVPX designs, negating some of the savings that come from using a backplane overlay.
A new technology, connector-less micro-overlays, presents a cost-effective solution that can also supply the necessary signal integrity to meet this challenge. Micro-overlays use BGA solder connection technology to interface a PCB-based differential pair matrix with compatible backplanes. The “micro” nature of the overlay reduces the transmission line impedance variations and “stubs” associated with connector-based interfaces by connecting directly to the main backplane via a solder interface. This advanced technique improves the signal integrity between system cards beyond the requirements of the PCI Express, Serial Rapid I/O and 10Gbit (XAUI) Ethernet standards (Figure 2).
A Practical Example
Figure 3
FMM micro-overlays also provide a natural migratory development environment for moving from the lab to the field with the high-speed backplanes
Dawn VME Products has enhanced the micro-overlay approach with a patent-pending Fabric Mapping Module (FMM) technology that simplifies and automates the optimization of backplane topologies in compliance with OpenVPX profiles. FMM allows designers to work with flexible configurations of high-speed links, so inter-slot communications can be customized to meet unique system requirements. These micro-overlays can also facilitate rear transition modules and low profile connector interface systems when normal transition modules do not fit the system application envelope.
FMM micro-overlays allow off-the-shelf backplanes to be quickly customized to mission requirements, without the time and expense required to spin a new backplane. This can be a critical advantage when schedules are compressed by late design changes, as described in the example above. Dawn’s FMM micro-overlays also provide a natural migratory development environment for moving from the lab to the field with the high-speed backplanes due to the rugged , low mass, connector-less characteristics of the technology (Figure 3).
OpenVPX profiles enable system designers to confidently create systems using components from multiple vendors, and the range of definable profiles allows a wide range of choices in connection standards and topologies. However, the profiles also introduce a new level of complexity to the design process, especially with regard to backplane profiles. During a design, this complexity issue adds to the already time-consuming task of creating a system backplane. Backplane micro-overlays offer a cost-effective and time-efficient method for customizing an OpenVPX backplane. They support the interoperability of OpenVPX, while providing the flexibility to quickly modify designs based on off-the-shelf backplanes.
Dawn VME Products, San Jose, CA. (510) 657-4444.
